PIC16F627-04/P【PDF 126/170 页】IC MCU FLASH 1KX14 COMP 18DIP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3873

122页 123页 124页 125页 [126页]127页 128页 129页 130页

2003 Microchip Technology Inc.

Preliminary

DS40300C-page 57

PIC16F62X

9.6

Comparator Interrupts

The Comparator Interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<6>, is the Comparator Interrupt Flag.

The CMIF bit must be RESET by clearing ‘0’. Since it is

also possible to write a '1' to this register, a simulated

interrupt may be initiated.

The

CMIE

bit

(PIE1<6>)

and

the

PEIE

bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are clear, the interrupt is not enabled, though the

CMIF bit will still be set if an interrupt condition occurs.

The user, in the interrupt service routine, can clear the

interrupt in the following manner:

Any write or read of CMCON. This will end the

mismatch condition.

Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow flag bit CMIF to be cleared.

9.7

Comparator Operation During

SLEEP

When a comparator is active and the device is placed

in SLEEP mode, the comparator remains active and

the interrupt is functional if enabled. This interrupt will

wake-up the device from SLEEP mode when enabled.

While the comparator is powered-up, higher SLEEP

currents than shown in the power-down current

specification will occur. Each comparator that is

operational will consume additional current as shown in

the comparator specifications. To minimize power

consumption while in SLEEP mode, turn off the

comparators, CM<2:0> = 111, before entering SLEEP.

If the device wakes-up from SLEEP, the contents of the

CMCON register are not affected.

9.8

Effects of a RESET

A device RESET forces the CMCON register to its

RESET state. This forces the Comparator module to be

in the comparator RESET mode, CM2:CM0 = 000.

This ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at RESET time. The comparators will be

powered-down during the RESET interval.

9.9

Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 9-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to V

and V

SS. The analog input therefore, must be between

SS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latchup may occur. A

maximum

source

impedance

10 k

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

Note:

If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR1<6>)

interrupt flag may not get set.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式